Embodiments of the inventive concept relate to domino logic circuits, and more particularly, to pseudo-static NP domino logic circuits capable of more accurately processing data with increased processing speed. Embodiments of the inventive concept also relate to apparatuses including this type of domino logic circuit.
Domino logic circuits are well known in the field of digital logic circuitry. It is not uncommon for a domino logic circuit to be used in the critical path of a processor or similar computational logic circuit where low data latency is an important design factor. The design of digital logic systems and data processing systems is usually a matter of trade-offs between computational speed, computational accuracy, physical size, power consumption, etc. Indeed, the use of domino logic circuit(s) in many contemporary systems is motivated by the relative ability of such circuits to provide acceptable performance with relatively reduced size and power consumption.
However, domino logic circuits are not without their design, implementation and operation problems. For example, the “pulsed” nature of domino logic circuit signals leads to well understood problems associated with input pulse overlap and domino gate output hold timing at clock cycle boundaries. Multiple conventional attempts to address these problems have resulted in undesirably large domino logic circuits and/or undue power consumption. Where multiple phase, over-lapping clock signals are used to address the noted problems, circuit complexity rises along with circuit size and power consumption. Other conventional attempts to convert early phase domino pulses into static signal using a so-called “staticizing” latches in order to avoid hold timing issues only results in signal processing delays as well as power and size problems.
Nonetheless, as the operating speed of contemporary processors and digital logic circuits increases, the demand for faster, smaller, and better-performing domino logic circuits continues.